1. Field of the Invention
This invention relates to integrated circuit fabrication and more particularly to NMOS integrated circuits having short channel lengths and a threshold adjust implant.
2. Description of the Relevant Art
Fabrication of an MOS device is well known. Generally speaking, MOS devices are manufactured by placing a polysilicon material over a relatively thin gate oxide, patterning the polysilicon material, and thereafter implanting the patterned polysilicon and adjacent source/drain regions with an impurity dopant material. If the impurity dopant material used for forming the source/drain regions is n-type, then the resulting MOS device is an NMOS device. Conversely, if the source/drain dopant material is p-type, then the resulting MOS device is a PMOS device.
Fabrication of an NMOS device begins with a p-type substrate having n-type source/drain regions implanted therein. A channel region is formed within an upper layer of the substrate between corresponding pairs of source and drain regions. A patterned gate oxide and polysilicon (polysilicon trace element) are pre-formed above the channel in order to controllably activate an inversion area within the channel between source and drain junctions. In FIG. 1, a top view of a generalized MOS device 10 is shown having a polysilicon trace element 12 placed above channel region 14. Channel region 14 is configured between source/drain implants 16.
Very large scale integration (VLSI) processing dictates that devices 10 be placed close to one another in a dense fashion. As such, source/drain regions 16 are implanted at a shallow depth, and are separated from one another by a short channel region 14. The distance between source/drain regions is often referred to as the "physical channel length". However, after implantation and subsequent diffusion of the source/drains, the distance between the source/drain regions 16 becomes less than the physical channel length, and is often referred to as the "effective channel length" (Leff).
Referring to a cross-sectional view along plane A--A of FIG. 1, FIG. 2 illustrates Leff as the distance between the inner diffusion boundaries of source/drain regions 16. As MOS devices become more dense, Leff becomes extremely small. A well-known phenomena, denoted as "short channel effects" (SCE) generally arises whenever Leff becomes less than approximately 2.0 .mu.m. SCE becomes a dominant part of MOS device behavior at small Leffs. Generally speaking, SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing subthreshold currents. A problem associated with SCE, however, altogether different in operation from SCE, is the problem of "hot carrier effect" (HCE). HCE is a phenomena by which hot carriers (i.e., holes or electrons) can overcome the potential energy barrier between the silicon and overlying silicon dioxide (i.e., gate oxide) in order to cause hot carriers to inject into the gate oxide. HCE thereby relates to carrier impact at the substrate topography, whereas SCE relates to carrier impact within the substrate itself.
SCE is most pronounced by its affect upon threshold voltages. As Leff is reduced, measured value of threshold voltage of an NMOS enhancement-mode device becomes less positive, while threshold of an NMOS depletion-mode device becomes more negative. Hence, some of the channel region becomes partially depleted without any influence of a gate voltage. Since some of the channel is depleted absence gate bias, less gate charge is required to invert the channel in short-channel devices than in long-channel devices with comparable substrate doping. Another problem associated with SCE is the impact upon subthreshold currents. In short-channel devices, larger subthreshold current values are observed at lower voltages than in long-channel devices. Two of the primary causes of increased subthreshold current are: (i) punchthrough and (ii) drain-induced barrier lowering (DIBL). Punchthrough results from the widening of the drain depletion region when a reverse-biased voltage is placed on the drain. The electric field of the drain may eventually penetrate to the source area, thereby reducing the potential energy barrier of the source-to-body junction. Recent studies have indicated that in devices which use ion implantation to adjust threshold voltages, the barrier is lowest away from the silicon-silicon dioxide interface. As a result, punchthrough current appears to flow below the surface region and deep within the substrate bulk material. Contrary to punchthrough current, DIBL-induced current seems to occur mostly at the substrate surface. Application of a drain voltage can cause the surface potential to be lowered, resulting in a lowered potential energy barrier at the surface and causing the subthreshold current in the channel near the silicon-silicon dioxide interface to be increased. This implies that subthreshold current at the surface due to DIBL is expected to become larger as the gate voltage approaches threshold.
As shown above, there are numerous effects resulting from SCE including but not limited to threshold, punchthrough and DIBL skews. Unlike SCE, HCE occurs above the substrate in the substrate topography and, more particularly, mostly in the gate oxide. This is because the gate oxide normally contains empty electron states, also known as "traps", which can be filled by the injection of hot carriers. Due to the polarity of trapped charge, the resulting shift in the NMOS device threshold is positive. The result of HCE is therefore the same as SCE for threshold skew, but the means for achieving the deleterious result is altogether different. Further, HCE does not demonstrate bulk or surface-induced current such as punchthrough-induced current and DIBL-induced current.
The problems associated with NMOS devices are unique and dissimilar from PMOS devices. NMOS devices generally suffer from HCE to a greater degree than PMOS devices. Channel lengths smaller than, for example, 1.5 .mu.m make more severe the migration of hot carriers (i.e., electrons) to unwanted areas of the NMOS device. Hot electrons in NMOS devices are more mobile than hot holes in PMOS devices, making HCE a predominant problem in NMOS processing. A popular processing methodology used to minimize HCE is to apply double-diffused drains or lightly diffused drains (LDDs) in the active area. The purpose of LDDs is to absorb a majority of the electron potential into the drain and thus reduce the maximum electric field therein. Illustrated in FIG. 2 are LDDs 20 implanted into an active region 14 defined between field oxide areas 18. Field oxide 18 is selectively formed using, for example, the well-known local oxidation (often referred to as "LOCOS") process. Active regions are those regions which result from openings between locally oxidized field areas. A suitable field oxide insulation material includes silicon dioxide.
LDDs 20 are implanted into the active area after field oxide 18 and polysilicon 12 are formed, but before the formation of sidewall spacers 22. The purpose of sidewall spacers 22 at the sides of polysilicon element 12 is to ensure implant of source/drain 16 a spaced distance from the channel. Source/drain 16 are implanted at a higher dose than LDDs 20. Source/drain 16 implant species is preferably arsenic while LDD 20 implant species is preferably phosphorous. Lighter dose LDD implant absorbs virtually the entire voltage drop between the drain (or source) and the channel. The electric field is thereby reduced, resulting in a lessening of the hot carriers being injected into the gate oxide 24. As described in Ng, et al., "Suppression of Hot-Carrier Degradation in Si MOSFET's by Germanium Doping", Electron Device Letters, Vol. 11, No. 1, January, 1990, germanium co-implanted with the LDD areas further enhances the LDD structure. Germanium, being electrically neutral, is purposefully placed in the LDD areas in order to minimize injection of "lucky" hot carriers in the gate oxide.
A dissimilar phenomena from that of HCE and the LDD partial solution thereto, SCE often presents itself as punchthrough (bulk) current 26 and DIBL (surface) current 28 during subthreshold operations. In order to minimize punchthrough current along path 26, substantial research has focused upon using germanium co-implanted with the source/drain implant. See, e.g., Pfiester, et al., "Improved MOSFET Short Channel Device Using Germanium Implantation", IEEE Electron Device Letters, Vol. 9, No. 7, July, 1988. Germanium is therefore known as having an inhibiting effect upon junction depths, thereby providing reduced punchthrough current in the substrate bulk. More recent studies with fluorine indicates the retardant effect of fluorine upon both the junction depth as well as the lateral diffusion of the source/drain junction. See, e.g., Lin, et al., "The Effect of Fluorine on MOSFET Channel Length", IEEE Electron Device Letters, Vol. 14, No. 10, October, 1993.
While co-implant of a barrier material in the LDD appears to inhibit hot carrier injection and co-implant of the barrier material within the source/drain appears to inhibit subthreshold punchthrough current, additional solutions are needed, however, to inhibit DIBL-induced current along path 28. Dissimilar from the problems of HCE and punchthrough current, DIBL-induced current arises primarily from the operation of, or voltage placed upon, the drain region. A popular technique used to minimize DIBL-induced current typically involves placing a threshold adjust implant at the substrate surface in order to minimize DIBL-induced current therethrough. Boron is often lightly implanted at the substrate surface of an NMOS device, as shown by reference numeral 30, in order not only to increase threshold voltages in channel 14, but also to offset the lowering of the surface potential naturally resulting from drain bias. As the gate voltage approaches threshold, DIBL-induced subthreshold current will be lowered as a result of boron threshold adjust implant 30. Boron, being of relatively small atomic mass, as compared to, e.g., arsenic or phosphorous, is more mobile during processing steps subsequent to its implant. Movement of boron in region 30 from channel 14 to adjacent LDD 20 and/or source/drain 16 is often termed "boron redistribution and segregation". Many studies have evidenced this occurrence in NMOS device formation and have attributed its result to threshold rolloff and DIBL-induced current. See, e.g., Acovic, et al., "Arsenic Source and Drain Implant-Induced Degradation of Short-Channel Effects in NMOSFET's", IEEE Electron Device Letters, Vol. 14, No. 7, July, 1993.
As a result of recent discoveries, the advantages of boron implant 30 necessary to minimize DIBL-induced current are offset by boron migration from channel 14 and the problems resulting therefrom. While arsenic provides higher conductivity in the active source/drain areas 16, it also disrupts or damages the substrate lattice to a greater extent than lower atomic mass n-type implants such as phosphorous. In order to remove the damage caused by arsenic implant, higher temperature anneal at approximately 900.degree. C. to 1100.degree. C. is oftentimes necessary. In the course of annealing, boron atoms 32, shown in FIG. 3 (i.e., FIG. 3 being a detailed view along area C of FIG. 2), migrate or diffuse (segregate) from the edges of channel region 14 to LDD 20 and/or source/drain 16. The boron atoms can diffuse across substitutional (or vacant) sites or through interstitial movement. Vacancies in regions 20 and 16 caused by phosphorous atom 33 (in LDD region) and arsenic atom 34 (in source/drain region) implant brings about a large amount of intra-lattice disruptions at the implant site. Those disruptions greatly enhance interstitialcy and/or substitutional motion of lighter atomic species, such as the boron threshold adjust implant species, from edge of channel 14 to adjacent LDD regions 20 and source/drain regions 16.
While it is important to incorporate a threshold adjust implant step during NMOS processing using, for example, boron implant 30, it is also important to minimize the segregation and redistribution of boron atoms 32 within implant region 30 from channel 14 to adjacent source/drain region 16 and/or LDD region 20. One way in which to minimize boron redistribution and segregation is to implant an electrically inactive barrier atom along with the LDD implant or source/drain implant. By co-implanting an electrically inactive ion such as germanium, as described above, the barrier material effectively "plugs" redistribution avenues through which the migratory boron atoms 32 might take. For the same reason that germanium is an effective barrier species due to its large atomic mass, germanium unfortunately exacerbates the redistribution problems as a result of its implant. During implant, large germanium ions adds lattice disruption within the silicon substrate as a result of germanium nuclear collisions with the silicon target. The nuclear collision of large germanium ions displaces the target silicon atoms causing disorder within the substrate lattice. A prevalent amount of "sink" areas of boron bonding opportunities are thereby created in the source/drain 16 and/or LDD 20 regions as a result of the germanium ion impact.
Using a large atomic mass barrier dopant species adds an unacceptable amount of lattice disruption in the source/drain region 16 and LDD region 20. Instead of minimizing segregation and redistribution of boron from channel 14, additional lattice disruption caused by barrier implant has, in effect, an adverse boron distribution affect. If boron is allowed to redistribute to implant-damaged areas, redistributed boron would, instead of minimizing the problem of subthreshold (DIBL-induced) current, compound the problem. The result of enhanced redistribution would be a threshold rolloff at the edges of channel 14.
Related to but in many instances different from the SCE phenomenon is another phenomenon known as "narrow gate-width effect" (NGWE). NGWE refers to the encroachment of channel stop dopant such as boron under the field oxide 18 at the sides of active region 14. Referring to FIG. 4, a cross-sectional view of the gate width along plane B--B of FIG. 1 is shown. Channel stop dopant 36 is typically placed across the upper surface of the substrate below field oxide 18. Channel stop dopant 36 is of opposite polarity type than the source/drain regions and, for NMOS devices, is generally boron. Boron of channel stop dopant 36 is placed during or separate from the boron implanted within threshold adjust region 30. Channel stop dopant 36 is placed in most conventional processing steps prior to growth of field oxide 18. Channel stop dopant 36 thereby serves to adjust the threshold voltage in the field regions to prevent what is commonly referred to as "field inversion". Increase in device density results in a shortening of channel lengths as well as channel widths. As channel widths decrease, there appears a greater likelihood that source/drain voltages and channel voltage will cause field-induced encroachment of dopants 36 into the adjacent channel 14. Encroachment, shown by arrow 40 provides an even smaller channel width, i.e., a channel width, Wmod, which is less than the physical channel width, W. Encroachment appears a natural, yet unwanted result of boron segregation and redistribution from the field areas underneath field oxide 18 to channel areas 14.
A combination of out-migration of boron from channel 14 to source/drain 18 and in-migration of boron from field areas to channel 14 leaves a boron concentration skew or gradient across channel 14. Out-migration of boron from channel 14 as a result of the "sink" locations within the implanted source/drain regions is illustrated in reference to FIG. 5a. FIG. 5a exemplifies a threshold gradient across a channel length (L). At both edges of the channel length (L=0 and L=L.sub.max), boron concentration is lessened as a result of out-migration causing a lowering of threshold (i.e., rolloff) at two opposing first pair of channel edges. FIG. 5b exemplifies a threshold gradient across a channel width (W). At both edges of the channel length (W=0 and W=W.sub.max), boron concentration is heightened as a result of in-migration causing an increase in threshold at two opposing second pair of channel edges. The in-migration of boron and heightening of threshold along the second pair of channel edges appears as not being as critical a problem in short channel devices as boron out-migration and threshold rolloff. In the former instance shown in FIG. 5a, lessening of threshold occurs at the edges of the channel region, whereas, in the latter instance shown in FIG. 5b, lessening of threshold occurs in the edges of the field region underneath field oxide 18. Lessening of threshold in the channel may cause inadvertent turn-on or cause large subthreshold currents of the DIBL variety, and lessening of threshold in the field may cause inadequate electrical isolation and field inversion which in some instances can be compensated for by a thicker field oxide.